1. Technical Field
Example embodiments relate to a semiconductor device and a method of forming the same. Example embodiments also relate to a method of forming a semiconductor device having an offset spacer and a related device.
2. Description of the Related Art
As higher integration is expected of semiconductor devices, research has been conducted to reduce transistor size. A transistor may include a gate electrode disposed on a semiconductor substrate and a pair of source and drain regions spaced apart from each other. The source and drain regions may be respectively disposed within the semiconductor substrate and may be adjacent to both sides of the gate electrode. However, reducing the gate electrode so as to reduce transistor size may result in a short channel effect. Consequently, a technique of forming an offset spacer on sidewalls of the gate electrode has been proposed to reduce or prevent the short channel effect. In such a case, the source and drain regions may be arranged outside the coverage of the offset spacer. As a result, the effective channel length of the transistor having the offset spacer may be lengthened.
FIGS. 1 and 2 are cross-sectional views illustrating a method of forming a conventional semiconductor device having an offset spacer. Referring to FIG. 1, a gate dielectric layer 13 and a gate electrode 15 may be sequentially stacked on a semiconductor substrate 11. A spacer layer 17 may be formed on the semiconductor substrate 11 having the gate electrode 15. The spacer layer 17 may cover the sidewalls of the gate electrode 15 and the surface of the semiconductor substrate 11. The spacer layer 17 may be formed of silicon oxide.
Referring to FIG. 2, an offset spacer 17′ may be formed by anisotropically etching the spacer layer 17. The offset spacer 17′ may cover the sidewalls of the gate electrode 15. A by-product P (e.g., a polymer) may be produced during the process of anisotropically etching the spacer layer 17 and may adhere to the semiconductor substrate 11. The by-product P may hinder the performance of subsequent processes (e.g., formation of lightly-doped drain (LDD) regions).
For example, forming the LDD regions may include implanting impurity ions into the semiconductor substrate 11 using the gate electrode 15 and the offset spacer 17′ as an ion implantation mask. However, the by-product P may have a non-uniform thickness and may cover the semiconductor substrate 11. Thus, the by-product P may hinder the implantation of impurity ions into the semiconductor substrate 11. Accordingly, the LDD regions may exhibit a non-uniform impurity concentration. LDD regions having a non-uniform impurity concentration may have different threshold voltages from each other. As a result, it may be difficult to control the threshold voltages of transistors disposed on the semiconductor substrate 11.
A technique of removing the by-product P by performing a cleaning process on the semiconductor substrate 11 may be employed. However, a surface of the semiconductor substrate 11 may be etched during the cleaning process so as to from a recess region 11R. The recess region 11R may change the effective channel length and may also have an effect on the junction depth.
Another method of forming a semiconductor device having an offset spacer may include forming a gate electrode on a semiconductor substrate. A polysilicon re-oxidation layer covering the electrode and the semiconductor substrate may be formed. An offset spacer may be formed on sidewalls of the gate electrode. The offset spacer may be formed of a nitride layer. The polysilicon re-oxidation layer may reduce or prevent the etching of the semiconductor substrate during the formation of the offset spacer.
However, the gate electrode may be formed of polysilicon, and the semiconductor substrate may be a single crystalline silicon wafer. Additionally, the polysilicon re-oxidation layer may be formed by a thermal oxidation method. Consequently, the polysilicon re-oxidation layer formed on the single crystalline silicon wafer may be thinner than the polysilicon re-oxidation layer formed on the sidewalls of the gate electrode. Accordingly, it may be very difficult to control the thickness of the polysilicon re-oxidation layer.